First off: this is not going to be an introduction to VHDL or Verilog, the two languages normally used to define the configuration of an FPGA. There are books for that, it’s a huge field, and yours truly isn’t really versed enough in either of them… not yet, anyway.
Let’s simply explore this whole domain a bit. Enough to get a feel for what’s involved.
At the most basic level, you might expect a structural definition of the entire circuit, i.
↧