To check that the eZ80 chip works, we only need to connect it to the Blue Pill with 6 wires:
- +3.3V and ground (the eZ80 runs at 3.3V, but it has 5V-tolerant I/O pins)
- a two-wire “Zilog Debug Interface” (ZDI), which is a bit like JTAG, but simpler
- a clock signal to drive the eZ80 (anything from DC up to 50 MHz)
- a reset signal - not strictly necessary, but convenient
See the README for the exact connections used in this project.
Here is a meticulously soldered eZ80 on a QFP-144 breakout PCB, connected to a Blue Pill:
There are about a dozen pins which need to be connected to ground, and another dozen pins connected to 3.3V. Each of these has been decoupled with a 0.1 µF SMD capacitor, soldered between the corresponding pins around the perimeter.
For the clock signal, let’s start by generating a 8 MHz signal with a timer in the STM32F103, dividing the 72 MHz system clock by 9, and set it up to generate a roughly 45% duty cycle.
For ZDI, we need 2 primitives: >zdi to write a byte to a register, and zdi>
to read a byte from a register. This can be implemented with these 8 words and
two dozen lines of Forth code:
: zdi-init ... ;
: delay 10 0 do loop ;
: zcl-lo delay ZCL ioc! delay ;
: zcl-hi delay ZCL ios! delay ;
: zdi! ( f -- ) zcl-lo ZDA io! zcl-hi ZDA ios! ;
: zdi-start ( u -- ) ... ;
: zdi> ( addr -- val ) ... ;
: >zdi ( val addr -- ) ... ;
Everything else is built on top of these. For example, to get the eZ80 chip version, we can do:
: v 0 zdi> h.2 space 1 zdi> h.2 space 2 zdi> h.2 space ; ok
v 08 00 02 ok.
What this confirms, is that the eZ80 is indeed working, but there’s very little we can do with it, other than peek and poke around in the on-board memory, and run individual instructions.
Given that 16 KB on-board SRAM is not sufficient to run CP/M, and that it isn’t even located at address $0000 in memory, an external static RAM chip is really unavoidable for actual use.
And while we’re at it, let’s also connect one serial port from the eZ80 to one on the Blue Pill:
There are a lot of (short) wires involved! The 512 KB SRAM chip used here has 8 data lines, 19 address lines, 3 control lines, and 3.3V/GND. To avoid problems with the power supplied by the Blue Pill’s 3.3V regulator, two 10 µF capacitors have also been added to the circuit.
The SRAM used here is a fast 10 ns chip, which should allow running the eZ80 at its maximum speed of 50 MHz later on, without having to use wait states to slow down memory access.
There is also a 2048 KB version of this chip, in the same package, just two more address pins. EZ-Retro will work with either one. With 2048K, we can implement an extra RAM drive.
So much for the hardware side, at least as initial configuration.
The next step will be to prepare for CP/M: figuring out how to use available flash + RAM memory and how to bootstrap this concoction into a minimal working CP/M system.